Certain applications of programmable logic devices, such as military, aerospace, and high-reliability communications, must be able to operate reliably in environments subjected to various radiation effects caused by energetic heavy ions and subatomic particles striking the silicon. When an ion strikes a circuit, it may cause a glitch in a voltage at a node which may result in an unintentional state change in a data storage node. This is commonly known as soft error, or a single-event effect. Two of the most common single-event effects are single-event upsets (SEUs), which refer to the loss of data in a storage element caused by an ion striking the storage element directly, and single-event transients (SET), which refer to the loss of data caused by a glitch on the clock or other input signals as a result of an ion strike, changing the internal node voltages of the circuit for a short time interval.
D flip-flops (DFFs) are one type of memory element that is subject to upset from cosmic neutrons and terrestrial alpha particles. The failure rate associated with DFFs is known as the Soft Error Rate (SER), and the metric used to quantify the SER of a circuit is known as the Failure In Time (FIT) rate or FIT/Mb. In a typical field programmable gate array (FPGA) design, for example, the clock driving the DFF is most likely in a ‘0’ state when a failure occurs, i.e., indicating that the slave is in latch mode. However, because of modifications to the slave latch to reduce failures, there may be a significant mismatch in the load at the input and output nodes of the master latch when the master latch in in the latch mode, resulting in an increase of the overall DFF FIT rate.
It is desirable to reduce the overall FIT rate of DFFs in an integrated circuit.